Isolation device

ABSTRACT

An isolation device that can be used for providing optical and electrical isolation between areas of an integrated chip. The isolation device includes three doped elongate regions which form diodes which can be connected in series. The isolation device can be used in optical devices or optical attenuators.

[0001] This invention relates to an isolation device for providingoptical and electrical isolation between areas of an integrated opticalcircuit.

[0002] It is known to isolate two optically conductive areas of anintegrated optical circuit from each other by providing a trench betweenthe two areas. If the trench is empty, optical isolation is provided byreflection of stray light at the interface between the opticallyconductive area and the trench. It is preferable instead to absorb thestray light by filling the trench with light absorbent material.However, this may have a tendency of reducing the electrical isolationbetween the two optically conductive areas.

[0003] It is also known to absorb stray light by providing dopant inselected areas of an optical chip, e.g. as described in WO-A-99/28772,the disclosure of which is incorporated herein.

[0004] This invention aims to provide an alternative form of devicewhich provides both optical and electrical isolation.

[0005] According to the invention, there is provided an isolation devicefor providing optical and electrical isolation between areas of anintegrated optical chip comprising a first elongate region doped with afirst dopant material, a second elongate region on one side of the firstelongate region and a third elongate region on the opposite side of thefirst elongate region, the second and third elongate regions being dopedwith a second dopant material of opposite polarity to the first dopantmaterial so a first diode is formed between the second and firstelongate regions and a second diode is formed between the first andthird elongate regions, the first and second diodes being connected inseries with opposing polarity.

[0006] Preferred and optional features of the invention will be apparentfrom the following description and from the subsidiary claims of thespecification.

[0007] The invention will now be further described, merely by way ofexample, with reference to the accompanying drawings, in which:

[0008]FIG. 1 is a schematic cross-sectional view through a deviceaccording to one embodiment of the invention;

[0009]FIG. 2 is a schematic cross-sectional view through a deviceaccording to another embodiment of the invention; and

[0010]FIG. 3 is a schematic plan view of a variable optical attenuatorincorporating devices such as shown in FIGS. 1 and 2; and

[0011]FIG. 4 is a schematic cross-sectional view through a deviceaccording to a further embodiment of the invention.

[0012]FIGS. 1 and 2 show devices comprising an n-p-n junction formed inthe silicon layer of a silicon-on-insulator (SOI) chip comprises a layerof silicon 1, separated from a substrate 2 (which may also be ofsilicon) by an insulating layer 3, e.g. of silicon dioxide.

[0013] The silicon layer 1 is nominally intrinsic, i.e. with no n or pdoping, although in practice it tends to contain a very small amount ofp-dopant. FIG. 1 shows first and second areas 1A and 1B of the siliconlayer 1 which are separated by an n-p-n junction comprising an elongatep-doped region 4, a first elongate n-doped region 5 on one side thereofand a second elongate p-doped region 6 on the opposite side thereof. Theregions 4 and 5 thus form a first pn junction and the regions 4 and 6form a second pn junction, the two pn junctions being connected inseries (by the common p-doped region 4) with opposing polarity. It willbe appreciated that current may flow through a forward biased pnjunction but not through a reverse biased pn junction. Thus, even if anelectrical potential exists between the first area 1A and the secondarea 1B, no current can flow therebetween through the regions 4, 5 and 6as this potential will reverse bias one of the pn junctions. The n-p-njunction thus electrically isolates the first area 1A from the secondarea 1B. Furthermore, the dopant provided within the regions 4, 5 and 6absorbs stray light attempting to pass either from area 1A to area 1 Bor vice versa. The n-p-n junction thus also effectively opticallyisolates the area 1A from the area 1B.

[0014] As shown in FIG. 1, the p-doped region 4 and the n-doped regions5 and 6 preferably extend down to the oxide layer 3 (which iselectrically non-conductive) so there is no undoped silicon pathextending from area 1A to area 1B.

[0015] The doped regions 4, 5 and 6 may be fabricated by a variety ofknown methods involving ion implantation and/or diffusing in of dopantand may take forms other than those shown in FIG. 1. Each of the n-dopedregions 5 and 6 is shown contiguous with the p-doped region 4 so thereis no undoped silicon area therebetween. Alternatively, the adjacentregions may overlap to some extent (as shown in FIG. 2). Sucharrangements are suitable where the applied voltage is relatively lowand a compact layout is required.

[0016]FIG. 2 shows an alternative form of device in which a trench 7 isfirst etched in the silicon layer 1 prior to formation of the n-p-njunctions. The layer of silicon remaining at the base of the trench 7 isthus shallower so making it easier to form the doped region 4, 5 and 6through to the oxide layer 3.

[0017]FIG. 2 shows a thin silicon layer remaining beneath the dopedregions 4, 5 and 6 but, as indicated above, the doped regions 4, 5 and 6preferably extend through the entire depth of the silicon layer to theoxide layer 3.

[0018] In a typical SOI chip, the silicon layer 1 may have a thickness(from the surface of the chip to the oxide layer 3) of 4- 8 microns. Thetrench 7 is preferably etched to a depth such as to leave a layer ofsilicon at the base thereof of a thickness of around 2.6 microns.

[0019] The trench 7 may be etched deeper, or a further trench etched atthe base thereof, to reduce the thickness of silicon remaining furtherso long as the remaining layer of silicon has a sufficient thickness toenable the doped regions 4, 5 and 6 to be formed therein. However, inpractice, the trench may be formed at the same time as other etchedfeatures on the chip, e.g. p-i-n diodes (see below), so will be subjectto the minimum thickness requirements of these features, which mighttypically be 1 micron.

[0020] The depth of the trench 7, or the thickness of the silicon layerin which the n-p-n junction is formed, need not be in uniform across thedevice.

[0021] An isolation device such as that described above, may be used toprovide optical and electrical isolation between adjacent opticalwaveguides. For instance, a variable optical attenuator (VOA) maycomprise 40 or more channels and comprise an array of rib waveguidesformed in the silicon layer spaced from each other at a pitch of about250 microns. FIG. 3 shows a plan view of part of such a VOA comprising aplurality of rib waveguides 8 extending across a chip 9. Taperedsections 8A are provided at each end of the waveguides to facilitate alow loss coupling with an optical fibre (not shown). The taperedsections 8A may, for instance, be as described in U.S. Pat. No. 6108478.Attenuation devices 10 are provided on each waveguide 8 to providevariable attenuation of the optical signal carried by the waveguide 8.The attenuation device may, for instance, comprise one or more p-i-ndiode modulators, e.g., as described in U.S. Pat. No. 5757986 orco-pending application No. GB0019771.5 (Publication No. ______ ).Isolation devices 11 comprising n-p-n junctions as described above areprovided between each pair of waveguides 8 to provide electrical andoptical isolation between adjacent waveguides and their associatedattenuation devices 10. The devices are shown as comprising n-dopedregions 11A each side of a p-doped region 11B as described in relationto FIGS. 1 and 2.

[0022] In a further embodiment, especially where the electricalisolation to high voltages is required, e.g., in excess of 50V, thep-type and n-type regions are preferably separated by a relativelyundoped or intrinsic region. FIG. 4 shows such a form of device in whicha trench 7A is first etched in the silicon layer 1, prior to formationof n and p-type regions, 5A, 6A and 4A, separated by intrinsic regions12 so as to form a n-i-p-i-n junction. As previously indicated, the nand p-type doped regions preferably extend through the entire depth ofthe silicon layer to the oxide layer 3 to prevent any current leakageacross the junction between the regions 1A and 1B. The n-i-p-i-narrangement provides better reverse breakdown characteristics due to theshallower doping concentration gradient between the p and n-dopedregions, due to the intrinsic regions 12 therebetween.

[0023]FIG. 4 also shows a cross-section through a p-i-n diode attenuatordevice 10, such as that described above, on one side of the n-i-p-i-njunction.

[0024] The provision of an isolation device such as that described abovebetween adjacent waveguides can significantly reduce the cross-talkbetween the channels caused either by stray light passing from onewaveguide to another or electrical signals applied to an attenuator 10on one waveguide affecting the attenuators 10 on adjacent waveguides.

[0025] A device such as that shown in FIG. 1, FIG. 2 or FIG. 4, may,typically, have a width (i.e. the width of the n-p-n (or n-i-p-i-n)junction) in the range 20 microns to 50 microns. The n-p-n (orn-i-p-i-n) junction is formed by the elongate regions 4, 5 and 6 whichextend a required distance across the optical device. In the example ofa VOA mentioned above, they may, for instance, extend the entire lengthof the chip (as shown in FIG. 3), which may be a distance 20 mm or more.

[0026] It will be appreciated that a similar n-p-n (or n-i-p-i-n)junction may be formed in other types of chip to optically andelectrically isolate one are from another, e.g. a III/V material systemor other semiconductor material.

[0027] A p-n-p (or p-i-n-i-p) junction may be used in place of the n-p-n(or n-i-p-i-n) junctions described. If the nominally intrinsic siliconlayer 1 were slightly n-doped, this would be preferred.

[0028] The p-type dopant may typically comprise boron provided at adopant level of at least 10¹⁸cm⁻³, e.g., in the range of 10¹⁸ to 10²⁰cm⁻³, or higher.

[0029] The n-type dopant may typically comprise phosphorous provided ata dopant level of at least 10^(18 cm) ⁻³, e.g., in the range of 10¹⁸ to10²⁰ cm⁻³, or higher.

1. An isolation device for providing optical and electrical isolationbetween areas of an integrated optical chip comprising a first elongateregion doped with a first dopant material, a second elongate region onone side of the first elongate region and a third elongate region on theopposite side of the first elongate region, the second and thirdelongate regions being doped with a second dopant material of oppositepolarity to the first dopant material so a first diode is formed betweenthe second and first elongate regions and a second diode is formedbetween the first and third elongate regions, the first and seconddiodes being connected in series with opposing polarity.
 2. A device asclaimed in claim 1 comprising an optically conductive layer formed overan electrically non-conductive layer, the first, second and third dopedregions extending through the optically conductive layer to theelectrically non-conductive layer.
 3. A device as claimed in claim 1 or2 formed at the base of a trench formed in the surface of the opticalchip.
 4. A device as claimed in claim 1, 2 or 3 in which the second,first and third elongate regions form an n-p-n junction.
 5. A device asclaimed in any preceding claim in which the first elongate region isseparated from both the second and third elongate regions by arelatively undoped region.
 6. A device as claimed in any preceding claimformed on a silicon-on-insulator chip comprising a layer of siliconseparated from a substrate by a layer of insulating material.
 7. Adevice as claimed in claim 5 formed between two rib waveguides formed inthe silicon layer.
 8. An isolation device substantially as hereinbeforedescribed with reference to and/or as shown in FIG. 1 and/or FIG. 2and/or FIG. 4 of the accompanying drawings.
 9. An optical devicecomprising an array of waveguides with a device as claimed in any ofclaims 1-8 provided between adjacent waveguides.
 10. An optical devicesubstantially as hereinbefore described with reference to and/or asshown in FIG. 3 of the accompanying drawings.